275 search results - page 9 / 55 » Core architecture optimization for heterogeneous chip multip... |
HPCA
2007
IEEE
14 years 3 months ago
2007
IEEE
The significant speed-gap between processor and memory and the limited chip memory bandwidth make last-level cache performance crucial for future chip multiprocessors. To use the...
ICIP
1999
IEEE
14 years 10 months ago
1999
IEEE
A new chip-set for video display processing in a consumer television or set-top box is presented. Key aspect of the chip-set is a high flexibility and programmability of multi-win...
DSD
2008
IEEE
14 years 3 months ago
2008
IEEE
This paper proposes a system-level cycle-based framework to model and design heterogeneous Multiprocessor Systems on-Chip (MPSoC), called GRAPES. The approach features flexibilit...
IPPS
2007
IEEE
14 years 3 months ago
2007
IEEE
Hybrid chip multithreaded SMPs present new challenges as well as new opportunities to maximize performance. Our intention is to discover the optimal operating configuration of suc...
SIGARCH
2008
13 years 8 months ago
2008
- Bioinformatics applications such as gene and protein sequence matching algorithms are characterized by the need to process large amounts of data. While uni-processor performance ...