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CLUSTER
2009
IEEE
14 years 13 days ago
A scalable and generic task scheduling system for communication libraries
Abstract—Since the advent of multi-core processors, the physionomy of typical clusters has dramatically evolved. This new massively multi-core era is a major change in architectu...
François Trahay, Alexandre Denis
HPCA
2009
IEEE
14 years 8 months ago
Design and implementation of software-managed caches for multicores with local memory
Heterogeneous multicores, such as Cell BE processors and GPGPUs, typically do not have caches for their accelerator cores because coherence traffic, cache misses, and latencies fr...
Sangmin Seo, Jaejin Lee, Zehra Sura
CCS
2009
ACM
14 years 2 months ago
Secure in-VM monitoring using hardware virtualization
Kernel-level attacks or rootkits can compromise the security of an operating system by executing with the privilege of the kernel. Current approaches use virtualization to gain hi...
Monirul I. Sharif, Wenke Lee, Weidong Cui, Andrea ...
ISCA
2008
IEEE
135views Hardware» more  ISCA 2008»
14 years 2 months ago
ReVIVaL: A Variation-Tolerant Architecture Using Voltage Interpolation and Variable Latency
Process variations are poised to significantly degrade performance benefits sought by moving to the next nanoscale technology node. Parameter fluctuations in devices can introd...
Xiaoyao Liang, Gu-Yeon Wei, David Brooks
ASPLOS
2009
ACM
14 years 8 months ago
Mixed-mode multicore reliability
Future processors are expected to observe increasing rates of hardware faults. Using Dual-Modular Redundancy (DMR), two cores of a multicore can be loosely coupled to redundantly ...
Philip M. Wells, Koushik Chakraborty, Gurindar S. ...