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» Core-Selectability in Chip Multiprocessors
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ASPDAC
2010
ACM
163views Hardware» more  ASPDAC 2010»
15 years 2 months ago
A3MAP: architecture-aware analytic mapping for networks-on-chip
- In this paper, we propose a novel and global A3MAP (Architecture-Aware Analytic Mapping) algorithm applied to NoC (Networks-on-Chip) based MPSoC (Multi-Processor System-on-Chip) ...
Wooyoung Jang, David Z. Pan
ISCA
2011
IEEE
324views Hardware» more  ISCA 2011»
14 years 7 months ago
Prefetch-aware shared resource management for multi-core systems
Chip multiprocessors (CMPs) share a large portion of the memory subsystem among multiple cores. Recent proposals have addressed high-performance and fair management of these share...
Eiman Ebrahimi, Chang Joo Lee, Onur Mutlu, Yale N....
MICRO
2010
IEEE
121views Hardware» more  MICRO 2010»
15 years 1 months ago
Probabilistic Distance-Based Arbitration: Providing Equality of Service for Many-Core CMPs
Abstract--Emerging many-core chip multiprocessors will integrate dozens of small processing cores with an on-chip interconnect consisting of point-to-point links. The interconnect ...
Michael M. Lee, John Kim, Dennis Abts, Michael R. ...
RTSS
2007
IEEE
15 years 10 months ago
Response-Time Analysis for Globally Scheduled Symmetric Multiprocessor Platforms
In the last years, a progressive migration from single processor chips to multi-core computing devices has taken place in the general-purpose and embedded system market. The devel...
Marko Bertogna, Michele Cirinei
ICS
1999
Tsinghua U.
15 years 8 months ago
Improving the performance of speculatively parallel applications on the Hydra CMP
Hydra is a chip multiprocessor (CMP) with integrated support for thread-level speculation. Thread-level speculation provides a way to parallelize sequential programs without the n...
Kunle Olukotun, Lance Hammond, Mark Willey