27 search results - page 4 / 6 » Core-aware memory access scheduling schemes |
EUROSYS
2007
ACM
14 years 4 months ago
2007
ACM
The major chip manufacturers have all introduced chip multiprocessing (CMP) and simultaneous multithreading (SMT) technology into their processing units. As a result, even low-end...
ISCA
2002
IEEE
14 years 18 days ago
2002
IEEE
An increasingly large portion of scheduler latency is derived from the monolithic content addressable memory (CAM) arrays accessed during instruction wakeup. The performance of th...
ASPDAC
2006
ACM
14 years 1 months ago
2006
ACM
Abstract—H.264/AVC is the latest video coding standard. It significantly outperforms the previous video coding standards, but the extraordinary huge computation complexity and m...
NIS
1998
13 years 7 months ago
1998
The execution time of a large query depends mainly on the memory utilization which should avoid disk accesses for intermediate results. Poor memory management can hurt performance ...
HPCA
2009
IEEE
14 years 8 months ago
2009
IEEE
The number of functional errors escaping design verification and being released into final silicon is growing, due to the increasing complexity and shrinking production schedules ...