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» Core-aware memory access scheduling schemes
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TCSV
2008
129views more  TCSV 2008»
13 years 7 months ago
Efficient Architecture Design of Motion-Compensated Temporal Filtering/Motion Compensated Prediction Engine
Since motion-compensated temporal filtering (MCTF) becomes an important temporal prediction scheme in video coding algorithms, this paper presents an efficient temporal prediction ...
Yi-Hau Chen, Chih-Chi Cheng, Tzu-Der Chuang, Ching...
ISCA
2011
IEEE
386views Hardware» more  ISCA 2011»
12 years 11 months ago
Architecting on-chip interconnects for stacked 3D STT-RAM caches in CMPs
Emerging memory technologies such as STT-RAM, PCRAM, and resistive RAM are being explored as potential replacements to existing on-chip caches or main memories for future multi-co...
Asit K. Mishra, Xiangyu Dong, Guangyu Sun, Yuan Xi...
ECRTS
2010
IEEE
13 years 8 months ago
Making DRAM Refresh Predictable
Embedded control systems with hard real-time constraints require that deadlines are met at all times or the system may malfunction with potentially catastrophic consequences. Sched...
Balasubramanya Bhat, Frank Mueller
ISCA
2003
IEEE
110views Hardware» more  ISCA 2003»
14 years 29 days ago
Guided Region Prefetching: A Cooperative Hardware/Software Approach
Despite large caches, main-memory access latencies still cause significant performance losses in many applications. Numerous hardware and software prefetching schemes tolerate th...
Zhenlin Wang, Doug Burger, Steven K. Reinhardt, Ka...
ISCA
2012
IEEE
260views Hardware» more  ISCA 2012»
11 years 10 months ago
A case for exploiting subarray-level parallelism (SALP) in DRAM
Modern DRAMs have multiple banks to serve multiple memory requests in parallel. However, when two requests go to the same bank, they have to be served serially, exacerbating the h...
Yoongu Kim, Vivek Seshadri, Donghyuk Lee, Jamie Li...