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ISCA
2010
IEEE
336views Hardware» more  ISCA 2010»
15 years 6 months ago
Reducing cache power with low-cost, multi-bit error-correcting codes
Technology advancements have enabled the integration of large on-die embedded DRAM (eDRAM) caches. eDRAM is significantly denser than traditional SRAMs, but must be periodically r...
Chris Wilkerson, Alaa R. Alameldeen, Zeshan Chisht...
RTSS
2007
IEEE
15 years 8 months ago
ANDES: An ANalysis-Based DEsign Tool for Wireless Sensor Networks
— We have developed an analysis-based design tool, ANDES, for modeling a wireless sensor network system and analyzing its performance before deployment. ANDES enables designers t...
Vibha Prasad, Ting Yan, Praveen Jayachandran, Zeng...
130
Voted
MJ
2007
119views more  MJ 2007»
15 years 1 months ago
Automated energy calculation and estimation for delay-insensitive digital circuits
With increasingly smaller feature sizes and higher on-chip densities, the power dissipation of VLSI systems has become a primary concern for designers. This paper first describes...
Venkat Satagopan, Bonita Bhaskaran, Anshul Singh, ...
126
Voted
ESWS
2009
Springer
15 years 9 months ago
A Reasoning-Based Support Tool for Ontology Mapping Evaluation
In this paper we describe a web-based tool that supports the human in revising ontology alignments. Our tool uses logical reasoning as a basis for detecting conflicts in mappings ...
Christian Meilicke, Heiner Stuckenschmidt, Ondrej ...
130
Voted
DAC
2007
ACM
15 years 6 months ago
Verification Methodologies in a TLM-to-RTL Design Flow
SoC based system developments commonly employ ESL design ogies and utilize multiple levels of abstract models to provide feasibility study models for architects and development pl...
Atsushi Kasuya, Tesh Tesfaye