237 search results - page 15 / 48 » Cost-Efficient Memory Architecture Design of NAND Flash Memo... |
TVLSI
2002
13 years 7 months ago
2002
We propose a technique for reducing the energy spent in the memory-processor interface of an embedded system during the execution of firmware code. The method is based on the idea ...
DATE
2003
IEEE
14 years 1 months ago
2003
IEEE
We present a framework (Real-Time Calculus) for analysing various system properties pertaining to timing analysis, loads on various components and on-chip buffer memory requiremen...
ESORICS
2009
Springer
14 years 8 months ago
2009
Springer
1 There are increasing deployments of networked embedded systems and rising threats of malware intrusions on such systems. To mitigate this threat, it is desirable to enable common...
GLVLSI
2008
IEEE
2008
IEEE
Simultaneous optimization of memory configuration and code allocation for low power embedded systems
13 years 7 months ago
This paper proposes a hybrid memory architecture which consists of the following two regions; 1) a dynamic power conscious region which uses low Vdd and Vth and 2) a static power ...
DAC
1999
ACM
14 years 8 months ago
1999
ACM
In embedded system design, the designer has to choose an onchip memory configuration that is suitable for a specific application. To aid in this design choice, we present a memory...