127 search results - page 21 / 26 » Counter-Based Cache Replacement Algorithms |
SIGARCH
2008
13 years 9 months ago
2008
1 This paper presents a simple but effective method to reduce on-chip access latency and improve core isolation in CMP Non-Uniform Cache Architectures (NUCA). The paper introduces ...
IEEEPACT
2008
IEEE
14 years 4 months ago
2008
IEEE
One of the essential features in modern computer systems is context switching, which allows multiple threads of execution to time-share a limited number of processors. While very ...
IEEEPACT
2002
IEEE
14 years 2 months ago
2002
IEEE
In this paper, we describe an algorithm and implementation of locality optimizations for architectures with instruction sets such as Intel’s SSE and Motorola’s AltiVec that su...
LCPC
2007
Springer
14 years 4 months ago
2007
Springer
This paper describes the implementation of a runtime library for asynchronous communication in the Cell BE processor. The runtime library implementation provides with several servi...
ICS
2003
Tsinghua U.
14 years 3 months ago
2003
Tsinghua U.
Cache behavior modeling is an important part of modern optimizing compilers. In this paper we present a method to estimate the number of cache misses, at compile time, using a mac...