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» Counting in the Presence of Memory Faults
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DSN
2005
IEEE
13 years 9 months ago
Microarchitecture-Based Introspection: A Technique for Transient-Fault Tolerance in Microprocessors
The increasing transient fault rate will necessitate onchip fault tolerance techniques in future processors. The speed gap between the processor and the memory is also increasing,...
Moinuddin K. Qureshi, Onur Mutlu, Yale N. Patt
IPPS
1998
IEEE
13 years 11 months ago
Fault-Tolerant Message Routing for Multiprocessors
In this paper the problem of fault-tolerant message routing in two-dimensional meshes, with each inner node having 4 neighbors, is investigated. It is assumed that some nodes/links...
Lev Zakrevski, Mark G. Karpovsky
ICCAD
2005
IEEE
130views Hardware» more  ICCAD 2005»
14 years 4 months ago
A cache-defect-aware code placement algorithm for improving the performance of processors
— Yield improvement through exploiting fault-free sections of defective chips is a well-known technique [1][2]. The idea is to partition the circuitry of a chip in a way that fau...
Tohru Ishihara, Farzan Fallah
ICNS
2009
IEEE
13 years 5 months ago
HGRID: Fault Tolerant, Log2N Resource Management for Grids
Grid Resource Discovery Service is currently a very important focus of research. We propose a scheme that presents essential characteristics for efficient, self-configuring and fau...
Antonia Gallardo, Kana Sanjeevan, Luis Díaz...
DNA
2008
Springer
149views Bioinformatics» more  DNA 2008»
13 years 9 months ago
Connecting the Dots: Molecular Machinery for Distributed Robotics
Abstract. Nature is considered one promising area to search for inspiration in designing robotic systems. Some work in swarm robotics has tried to build systems that resemble distr...
Yuriy Brun, Dustin Reishus