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DDECS
2007
IEEE
105views Hardware» more  DDECS 2007»
14 years 1 months ago
A Heuristic for Concurrent SOC Test Scheduling with Compression and Sharing
1-The increasing cost for System-on-Chip (SOC) testing is mainly due to the huge test data volumes that lead to long test application time and require large automatic test equipmen...
Anders Larsson, Erik Larsson, Petru Eles, Zebo Pen...
ISSRE
2000
IEEE
13 years 12 months ago
Criteria for Testing Polymorphic Relationships
The emphasis in object-oriented programs is on defining abstractions that have both state and behavior. This emphasis causes a shift in focus from software units to the way softw...
Roger T. Alexander, A. Jefferson Offutt
DATE
2009
IEEE
98views Hardware» more  DATE 2009»
14 years 2 months ago
Test architecture design and optimization for three-dimensional SoCs
Core-based system-on-chips (SoCs) fabricated on threedimensional (3D) technology are emerging for better integration capabilities. Effective test architecture design and optimizat...
Li Jiang, Lin Huang, Qiang Xu
INTEGRATION
2006
102views more  INTEGRATION 2006»
13 years 7 months ago
A parameterized graph-based framework for high-level test synthesis
Improving testability during the early stages of high-level synthesis has several benefits including reduced test hardware overheads, reduced test costs, reduced design iterations...
Saeed Safari, Amir-Hossein Jahangir, Hadi Esmaeilz...
ECBS
2011
IEEE
274views Hardware» more  ECBS 2011»
12 years 7 months ago
Model-Driven In-the-Loop Validation: Simulation-Based Testing of UAV Software Using Virtual Environments
Abstract—With the availability of the off-the-shelf quadrocopter platforms, the implementation of autonomous unmanned aerial vehicle (UAV) has substantially been simplified. Suc...
Florian Mutter, Stefanie Gareis, Bernhard Schä...