68 search results - page 9 / 14 » Coverage in interpolation-based model checking |
DATE
2004
IEEE
13 years 11 months ago
2004
IEEE
Functional verification is widely acknowledged as a major bottleneck in microprocessor design. While early work on specification driven functional test program generation has prop...
CONCUR
1989
Springer
13 years 11 months ago
1989
Springer
In summary, RDL is an intuitionistic temporal logic for the specification of requirements and design of time-dependent systems. Coverage of RDL includes a backward chaining theore...
TACAS
2012
Springer
12 years 3 months ago
2012
Springer
FShell is an automated white-box test-input generator for C programs, computing test data with respect to user-specified code coverage criteria. The pillars of FShell are the decl...
DFG
2004
Springer
13 years 11 months ago
2004
Springer
This paper presents the real-time model checker RAVEN and related theoretical background. RAVEN augments the efficiency of traditional symbolic model checking with possibilities to...
DSD
2004
IEEE
13 years 11 months ago
2004
IEEE
Validation of programmable architectures, consisting of processor cores, coprocessors, and memory subsystems, is one of the major bottlenecks in current Systemon-Chip design metho...