1477 search results - page 146 / 296 » Criteria for the evaluation of implemented architectures |
KES
1998
Springer
14 years 2 months ago
1998
Springer
The architectural and circuit design aspects of a mixed analog/digital very large scale integration (VLSI) motion detection chip based on models of the insect visual system are des...
ICCD
1993
IEEE
14 years 2 months ago
1993
IEEE
Ravel-XL is a single-boardhardware accelerator for gate-level digital logic simulation. It uses a standard levelizedcode approach to statically schedule gate evaluations.However, u...
ICCAD
1994
IEEE
14 years 2 months ago
1994
IEEE
Existing built-in self test (BIST) strategies require the use of specialized test pattern generation hardware which introduces signi cant area overhead and performance degradation...
ASWEC
2007
IEEE
14 years 2 months ago
2007
IEEE
There is a growing demand for web applications to provide fair service to the highly concurrent requests. In this paper, we present an approach to addressing this requirement. Bas...
CAMP
2005
IEEE
14 years 6 days ago
2005
IEEE
— We have simulated the implementation of 16-bit floating point instructions on a Pentium4 and PowerPC G4 and G5 to evaluate the performance impact of these instructions in embed...