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NOCS
2008
IEEE
14 years 1 months ago
Reducing the Interconnection Network Cost of Chip Multiprocessors
This paper introduces a cost-effective technique to deal with CMP coherence protocol requirements from the interconnection network point of view. A mechanism is presented to avoid...
Pablo Abad, Valentin Puente, José-Án...
FCCM
2006
IEEE
131views VLSI» more  FCCM 2006»
14 years 1 months ago
Packet Switched vs. Time Multiplexed FPGA Overlay Networks
— Dedicated, spatially configured FPGA interconnect is efficient for applications that require high throughput connections between processing elements (PEs) but with a limited ...
Nachiket Kapre, Nikil Mehta, Michael DeLorimier, R...
SIGMETRICS
2011
ACM
191views Hardware» more  SIGMETRICS 2011»
12 years 10 months ago
Stability analysis of QCN: the averaging principle
Data Center Networks have recently caused much excitement in the industry and in the research community. They represent the convergence of networking, storage, computing and virtu...
Mohammad Alizadeh, Abdul Kabbani, Berk Atikoglu, B...
FPL
2008
Springer
153views Hardware» more  FPL 2008»
13 years 9 months ago
Exploring FPGA network on chip implementations across various application and network loads
Abstract-The network on chip will become a future general purpose interconnect for FPGAs much like today's standard OPB or PLB bus architectures. However, performance characte...
Graham Schelle, Dirk Grunwald
ISCA
1997
IEEE
137views Hardware» more  ISCA 1997»
13 years 11 months ago
VM-Based Shared Memory on Low-Latency, Remote-Memory-Access Networks
Recent technological advances have produced network interfaces that provide users with very low-latency access to the memory of remote machines. We examine the impact of such netw...
Leonidas I. Kontothanassis, Galen C. Hunt, Robert ...