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» Crosstalk Reduction in Area Routing
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ISQED
2007
IEEE
165views Hardware» more  ISQED 2007»
14 years 3 months ago
On-Line Adjustable Buffering for Runtime Power Reduction
We present a novel technique to exploit the power-performance tradeoff. The technique can be used stand-alone or in conjunction with dynamic voltage scaling, the mainstream techn...
Andrew B. Kahng, Sherief Reda, Puneet Sharma
ISPD
1997
ACM
110views Hardware» more  ISPD 1997»
14 years 1 months ago
Performance driven global routing for standard cell design
Advances in fabrication technology have resulted in a continual shrinkage of device dimensions. This has resulted in smaller device delays, greater resistance along interconnect w...
Jason Cong, Patrick H. Madden
ICCAD
2006
IEEE
122views Hardware» more  ICCAD 2006»
14 years 6 months ago
Network coding for routability improvement in VLSI
With the standard approach for establishing multicast connections over a network, network nodes are utilized to forward and duplicate the packets received over the incoming links....
Nikhil Jayakumar, Sunil P. Khatri, Kanupriya Gulat...
BROADNETS
2006
IEEE
13 years 11 months ago
On the Broadcast Storm Problem in Ad hoc Wireless Networks
Routing protocols developed for ad hoc wireless networks use broadcast transmission to either discover a route or disseminate information. More specifically, reactive routing proto...
Ozan K. Tonguz, Nawaporn Wisitpongphan, Jayendra S...
FPGA
2005
ACM
95views FPGA» more  FPGA 2005»
14 years 3 months ago
The Stratix II logic and routing architecture
This paper describes the Altera Stratix II™ logic and routing architecture. This architecture features a novel adaptive logic module (ALM) that is based on a 6-LUT, but can be p...
David M. Lewis, Elias Ahmed, Gregg Baeckler, Vaugh...