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» Crosstalk noise in FPGAs
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DAC
2005
ACM
14 years 8 months ago
Designing logic circuits for probabilistic computation in the presence of noise
As Si CMOS devices are scaled down into the nanoscale regime, current computer architecture approaches are reaching their practical limits. Future nano-architectures will confront...
Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, Will...
ISCAS
2003
IEEE
74views Hardware» more  ISCAS 2003»
14 years 27 days ago
Signaling capacity of FR4 PCB traces for chip-to-chip communication
The signaling capacity of traces on the popular PCB dielectric.material FR4 is under-utilized today by at least one order of magnitude through the choice of pre-coding, pulseshapi...
Marcus van Ierssel, Tooraj Esmailian, Ali Sheikhol...
FPL
2007
Springer
140views Hardware» more  FPL 2007»
14 years 1 months ago
An area-efficient alternative to adaptive median filtering in FPGAs
This paper presents a new approach to the FPGA implementation of image filters which are utilized to remove the saltand-pepper noise of high intensity (up to 70% of corrupted pix...
Zdenek Vasícek, Lukás Sekanina
ISQED
2003
IEEE
303views Hardware» more  ISQED 2003»
14 years 27 days ago
Design and Analysis of Low-Voltage Current-Mode Logic Buffers
- This paper investigates important problems involved in the design of a CML buffer as well as a chain of tapered CML buffers. A new design procedure to systematically design a cha...
Payam Heydari
FPL
2009
Springer
96views Hardware» more  FPL 2009»
14 years 7 days ago
Noise impact of single-event upsets on an FPGA-based digital filter
Field-programmable gate arrays are well-suited to DSP and digital communications applications. SRAM-based FPGAs, however, are susceptible to radiation-induced single-event upsets ...
Brian H. Pratt, Michael J. Wirthlin, Michael P. Ca...