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VLSID
2001
IEEE
118views VLSI» more  VLSID 2001»
14 years 7 months ago
Processor-Memory Co-Exploration driven by a Memory-Aware Architecture Description Language
Memory represents a major bottleneck in modern embedded systems. Traditionally, memory organizationsfor programmable systems assumed a fixed cache hierarchy. Withthe wideningproce...
Prabhat Mishra, Peter Grun, Nikil D. Dutt, Alexand...
IEEEPACT
2006
IEEE
14 years 1 months ago
Core architecture optimization for heterogeneous chip multiprocessors
Previous studies have demonstrated the advantages of single-ISA heterogeneous multi-core architectures for power and performance. However, none of those studies examined how to de...
Rakesh Kumar, Dean M. Tullsen, Norman P. Jouppi
HPCA
1998
IEEE
13 years 11 months ago
FPGA Based Custom Computing Machines for Irregular Problems
Over the past few years there has been increased interest in building custom computing machines (CCMs) as a way of achieving very high performance on specific problems. The advent...
David Abramson, Paul Logothetis, Adam Postula, Mar...
ERSA
2007
177views Hardware» more  ERSA 2007»
13 years 8 months ago
Energy-Aware System Synthesis for Reconfigurable Chip Multiprocessors
- Even though state-of-the-art FPGAs present new opportunities in exploring low-cost high-performance architectures for floating-point scientific applications, they also pose serio...
Xiaofang Wang, Sotirios G. Ziavras, Jie Hu
VLSID
2007
IEEE
104views VLSI» more  VLSID 2007»
14 years 7 months ago
Customization of Register File Banking Architecture for Low Power
Register file banking is an effective alternative to monolithic register files in embedded processor based systems. In this work, we propose techniques for performing application s...
Rakesh Nalluri, Rohan Garg, Preeti Ranjan Panda