39 search results - page 6 / 8 » DELTEST: Deterministic Test Generation for Gate-Delay Faults |
ATS
2009
IEEE
14 years 1 months ago
2009
IEEE
Caches are crucial components in modern processors (both stand-alone or integrated into SoCs) and their test is a challenging task, especially when addressing complex and high-fre...
DSD
2007
IEEE
14 years 2 months ago
2007
IEEE
This paper discusses possibilities for a choice of a pseudorandom pattern generator that is to be used in combination with the column-matching based built-in self-test design meth...
ATS
1998
IEEE
14 years 25 days ago
1998
IEEE
In mixed-mode BIST, deterministic test patterns are generated with on-chip hardware to detect the random-pattern-resistant (r.p.r.) faults that are missed by the pseudo-random pat...
DATE
1997
IEEE
14 years 3 days ago
1997
IEEE
A new method for state justi cation is proposed for sequential circuit test generation. The linear list of states dynamically obtained during the derivation of test vectors is use...
IPPS
2009
IEEE
14 years 3 months ago
2009
IEEE
Given a set of n different deterministic finite state machines (DFSMs) modeling a distributed system, we examine the problem of tolerating f crash or Byzantine faults in such a ...