Caches are crucial components in modern processors (both stand-alone or integrated into SoCs) and their test is a challenging task, especially when addressing complex and high-fre...
Wilson J. Perez, Danilo Ravotto, Edgar E. Sá...
This paper discusses possibilities for a choice of a pseudorandom pattern generator that is to be used in combination with the column-matching based built-in self-test design meth...
In mixed-mode BIST, deterministic test patterns are generated with on-chip hardware to detect the random-pattern-resistant (r.p.r.) faults that are missed by the pseudo-random pat...
Madhavi Karkala, Nur A. Touba, Hans-Joachim Wunder...
A new method for state justi cation is proposed for sequential circuit test generation. The linear list of states dynamically obtained during the derivation of test vectors is use...
Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. P...
Given a set of n different deterministic finite state machines (DFSMs) modeling a distributed system, we examine the problem of tolerating f crash or Byzantine faults in such a ...
Vinit A. Ogale, Bharath Balasubramanian, Vijay K. ...