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» DRAM reliability
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DAC
2009
ACM
14 years 12 months ago
Fault models for embedded-DRAM macros
In this paper, we compare embedded-DRAM (eDRAM) testing to both SRAM testing and commodity-DRAM testing, since an eDRAM macro uses DRAM cells with an SRAM interface. We first star...
Ching-Yu Chin, Hao-Yu Yang, Mango Chia-Tso Chao, R...
CODES
2011
IEEE
12 years 10 months ago
Memory controllers for high-performance and real-time MPSoCs: requirements, architectures, and future trends
Designing memory controllers for complex real-time and highperformance multi-processor systems-on-chip is challenging, since sufficient capacity and (real-time) performance must b...
Benny Akesson, Po-Chun Huang, Fabien Clermidy, Den...
ISCA
2012
IEEE
281views Hardware» more  ISCA 2012»
12 years 1 months ago
LOT-ECC: Localized and tiered reliability mechanisms for commodity memory systems
Memory system reliability is a serious and growing concern in modern servers. Existing chipkill-level memory protection mechanisms suffer from several drawbacks. They activate a l...
Aniruddha N. Udipi, Naveen Muralimanohar, Rajeev B...
ASPLOS
2010
ACM
14 years 5 months ago
Dynamically replicated memory: building reliable systems from nanoscale resistive memories
DRAM is facing severe scalability challenges in sub-45nm technology nodes due to precise charge placement and sensing hurdles in deep-submicron geometries. Resistive memories, suc...
Engin Ipek, Jeremy Condit, Edmund B. Nightingale, ...
MR
2002
75views Robotics» more  MR 2002»
13 years 10 months ago
DRAM reliability
Kinam Kim, Gi-Tae Jeong, Chan-Woong Chun, Sam-Jin ...