148 search results - page 16 / 30 » DRAMSim2: A Cycle Accurate Memory System Simulator |
TASE
2011
IEEE
13 years 2 months ago
2011
IEEE
—For multiclass flow line models, we identify a class of service times that allow a decomposition of the system into subsets of servers called channels. In each channel, the cus...
IISWC
2009
IEEE
14 years 2 months ago
2009
IEEE
— Programming to exploit the resources in a multicore system remains a major obstacle for both computer and software engineers. Transactional memory offers an attractive alternat...
DFT
2005
IEEE
14 years 1 months ago
2005
IEEE
Sequential elements, flip-flops, latches, and memory cells, are the most vulnerable components to soft errors. Since state-of-the-art designs contain millions of bistables, it i...
GLVLSI
2007
IEEE
14 years 1 months ago
2007
IEEE
The path-delay fault simulation of functional tests on complex circuits such as current processor-based systems is a daunting task. The amount of computing power and memory needed...
INFOCOM
2006
IEEE
14 years 1 months ago
2006
IEEE
In this paper, we present a high fidelity and efficient emulation framework called TWINE, which combines the accuracy and realism of emulated and physical networks and the scala...