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DATE
2005
IEEE
119views Hardware» more  DATE 2005»
14 years 1 months ago
Functional Validation of System Level Static Scheduling
Increase in system level modeling has given rise to a need for efficient functional validation of models above cycle accurate level. This paper presents a technique for comparing...
Samar Abdi, Daniel D. Gajski
SIPS
2007
IEEE
14 years 1 months ago
Dynamic Channel Flow Control of Networks-on-Chip Systems for High Buffer Efficiency
System-on-Chip (SoC) designs become more complex nowadays. The communication between each processing element often suffers challenges due to the wiring problem. Networks-on-Chip (...
Sung-Tze Wu, Chih-Hao Chao, I-Chyn Wey, An-Yeu Wu
IPPS
2007
IEEE
14 years 1 months ago
Cost-Driven Hybrid Configuration Prefetching for Partial Reconfigurable Coprocessor
Reconfigurable computing systems have developed the capability of changing the configuration of the reconfigurable coprocessor multiple times during the course of a program. Howev...
Ying Chen, Simon Y. Chen
ICISP
2010
Springer
13 years 11 months ago
Total Variation Minimization with Separable Sensing Operator
Compressed Imaging is the theory that studies the problem of image recovery from an under-determined system of linear measurements. One of the most popular methods in this field i...
Serge L. Shishkin, Hongcheng Wang, Gregory S. Hage...
ISSS
2000
IEEE
91views Hardware» more  ISSS 2000»
13 years 12 months ago
Instruction-based System-level Power Evaluation of System-On-A-Chip Peripheral Cores
Various system-level core-based power evaluation approaches for core types like microprocessors, caches, main memories, and buses, have been proposed in the past. Approaches for o...
Tony Givargis, Frank Vahid, Jörg Henkel