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MICRO
1995
IEEE
140views Hardware» more  MICRO 1995»
13 years 11 months ago
A system level perspective on branch architecture performance
Accurate instruction fetch and branch prediction is increasingly important on today’s wide-issue architectures. Fetch prediction is the process of determining the next instructi...
Brad Calder, Dirk Grunwald, Joel S. Emer
WSC
1998
13 years 8 months ago
Effective Implementation of Cycle Time Reduction Strategies for Semiconductor Back-end Manufacturing
Using discrete-event simulation models, a study was conducted to evaluate the current production practices of a high-volume semiconductor back-end operation. The overall goal was ...
Joerg Domaschke, Steven Brown, Jennifer Robinson, ...
ASPDAC
2010
ACM
151views Hardware» more  ASPDAC 2010»
13 years 5 months ago
Source-level timing annotation for fast and accurate TLM computation model generation
This paper proposes a source-level timing annotation method for generation of accurate transaction level models for software computation modules. While Transaction Level Modeling ...
Kai-Li Lin, Chen Kang Lo, Ren-Song Tsay
SAMOS
2010
Springer
13 years 5 months ago
Power aware heterogeneous MPSoC with dynamic task scheduling and increased data locality for multiple applications
A new heterogeneous multiprocessor system with dynamic memory and power management for improved performance and power consumption is presented. Increased data locality is automatic...
Oliver Arnold, Gerhard Fettweis
RSP
2003
IEEE
103views Control Systems» more  RSP 2003»
14 years 24 days ago
An Instruction Throughput Model of Superscalar Processors
With advances in semiconductor technology, processors are becoming larger and more complex. Future processor designers will face an enormous design space, and must evaluate more a...
Tarek M. Taha, D. Scott Wills