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» Data Criticality in Network-On-Chip Design
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DATE
2004
IEEE
97views Hardware» more  DATE 2004»
14 years 1 months ago
A Formal Verification Methodology for Checking Data Integrity
Formal verification techniques have been playing an important role in pre-silicon validation processes. One of the most important points considered in performing formal verificati...
Yasushi Umezawa, Takeshi Shimizu
TASLP
2002
110views more  TASLP 2002»
13 years 9 months ago
Automatic generation of subword units for speech recognition systems
Large vocabulary continuous speech recognition (LVCSR) systems traditionally represent words in terms of smaller subword units. Both during training and during recognition, they re...
Rita Singh, Bhiksha Raj, Richard M. Stern
HPCA
2008
IEEE
14 years 10 months ago
Performance and power optimization through data compression in Network-on-Chip architectures
The trend towards integrating multiple cores on the same die has accentuated the need for larger on-chip caches. Such large caches are constructed as a multitude of smaller cache ...
Reetuparna Das, Asit K. Mishra, Chrysostomos Nicop...
ISCA
1995
IEEE
120views Hardware» more  ISCA 1995»
14 years 1 months ago
Streamlining Data Cache Access with Fast Address Calculation
For many programs, especially integer codes, untolerated load instruction latencies account for a significant portion of total execution time. In this paper, we present the desig...
Todd M. Austin, Dionisios N. Pnevmatikatos, Gurind...
INFOCOM
2010
IEEE
13 years 8 months ago
Distributed Resource Allocation for Synchronous Fork and Join Processing Networks
—Many emerging information processing applications require applying various fork and join type operations such as correlation, aggregation, and encoding/decoding to data streams ...
Haiquan (Chuck) Zhao, Cathy H. Xia, Zhen Liu, Dona...