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» Data Criticality in Network-On-Chip Design
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ISCAS
2007
IEEE
173views Hardware» more  ISCAS 2007»
14 years 3 months ago
Critical Charge Characterization for Soft Error Rate Modeling in 90nm SRAM
— Due to continuous technology scaling, the reduction of nodal capacitances and the lowering of power supply voltages result in an ever decreasing minimal charge capable of upset...
Riaz Naseer, Younes Boulghassoul, Jeff Draper, San...
SECPERU
2006
IEEE
14 years 3 months ago
Detecting Critical Nodes for MANET Intrusion Detection Systems
Ad hoc routing protocols have been designed to efficiently reroute traffic when confronted with network congestion, faulty nodes, and dynamically changing topologies. The common d...
A. Karygiannis, E. Antonakakis, A. Apostolopoulos
ASPLOS
2009
ACM
14 years 10 months ago
Accelerating critical section execution with asymmetric multi-core architectures
To improve the performance of a single application on Chip Multiprocessors (CMPs), the application must be split into threads which execute concurrently on multiple cores. In mult...
M. Aater Suleman, Onur Mutlu, Moinuddin K. Qureshi...
BMCBI
2005
131views more  BMCBI 2005»
13 years 9 months ago
Critical evaluation of the JDO API for the persistence and portability requirements of complex biological databases
Background: Complex biological database systems have become key computational tools used daily by scientists and researchers. Many of these systems must be capable of executing on...
Marko Srdanovic, Ulf Schenk, Michael Schwieger, Fa...
DAC
2011
ACM
12 years 9 months ago
AENEID: a generic lithography-friendly detailed router based on post-RET data learning and hotspot detection
In the era of deep sub-wavelength lithography for nanometer VLSI designs, manufacturability and yield issues are critical and need to be addressed during the key physical design i...
Duo Ding, Jhih-Rong Gao, Kun Yuan, David Z. Pan