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ISCAS
2008
IEEE
102views Hardware» more  ISCAS 2008»
14 years 4 months ago
Asynchronous balanced gates tolerant to interconnect variability
Abstract— Existing methods of gate level power attack countermeasures depend on exact capacitance matching of the dual-rail data outputs of each gate. Process variability and a l...
Konrad J. Kulikowski, Vyas Venkataraman, Zhen Wang...
ISCAS
2006
IEEE
94views Hardware» more  ISCAS 2006»
14 years 4 months ago
On the sensitivity of BDDs with respect to path-related objective functions
— Reduced ordered Binary Decision Diagrams (BDDs) are a data structure for efficient representation and manipulation of Boolean functions. They are frequently used in logic synt...
Rüdiger Ebendt, Rolf Drechsler
SIGMETRICS
2004
ACM
14 years 3 months ago
Insensitive load balancing
A large variety of communication systems, including telephone and data networks, can be represented by so-called Whittle networks. The stationary distribution of these networks is...
Thomas Bonald, Matthieu Jonckheere, Alexandre Prou...
MKM
2004
Springer
14 years 3 months ago
CPoint: Dissolving the Author's Dilemma
Abstract. Automated knowledge management techniques critically depend on the availability of semantically enhanced documents which are hard to come by in practice. Starting from a ...
Andrea Kohlhase, Michael Kohlhase
GLVLSI
2000
IEEE
116views VLSI» more  GLVLSI 2000»
14 years 2 months ago
Reducing bus transition activity by limited weight coding with codeword slimming
Transitions on high capacitance busses in VLSI systems result in considerable power dissipation. Various coding schemes have been proposed in literature to encode the input signal...
Vijay Sundararajan, Keshab K. Parhi