1327 search results - page 45 / 266 » Data Dependent Circuit Design: A Case Study |
ISMVL
1997
IEEE
14 years 8 days ago
1997
IEEE
This paper shows how the application of a CMOS ternary logic is useful in the realisation of Delay Insensitive (01)asynchronous circuits. It is shown that fully DIasynchronous cir...
DATE
2002
IEEE
14 years 1 months ago
2002
IEEE
In this work, the problem of open faults affecting the interconnections of SC circuits composed by data-path and control is analyzed. In particular, it is shown that, in case open...
EURODAC
1994
IEEE
14 years 5 days ago
1994
IEEE
In performance-driven interconnect design, delay estimators are used to determine both the topology and the layout of good routing trees. We address the class of moment-matching, ...
DATE
2006
IEEE
14 years 2 months ago
2006
IEEE
This paper presents an innovative approach for analogue and mixed-signal verification. It consists in a “verification kit” that makes use of concepts used in state-of-art digi...
DSN
2008
IEEE
14 years 2 months ago
2008
IEEE
This paper proposes a formally well-rooted and extensible framework for dependability evaluation: Arcade (architectural dependability evaluation). It has been designed to combine ...