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» Data Dependent Circuit Design: A Case Study
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CORR
2006
Springer
112views Education» more  CORR 2006»
13 years 9 months ago
High-level synthesis under I/O Timing and Memory constraints
The design of complex Systems-on-Chips implies to take into account communication and memory access constraints for the integration of dedicated hardware accelerator. In this paper...
Philippe Coussy, Gwenolé Corre, Pierre Bome...
CF
2005
ACM
13 years 11 months ago
Drowsy region-based caches: minimizing both dynamic and static power dissipation
Power consumption within the memory hierarchy grows in importance as on-chip data caches occupy increasingly greater die area. Among dynamic power conservation schemes, horizontal...
Michael J. Geiger, Sally A. McKee, Gary S. Tyson
DOCENG
2010
ACM
13 years 10 months ago
Linking data and presentations: from mapping to active transformations
Modern GUI toolkits, and especially RIA ones, propose the concept of binding to dynamically link domain data and their presentations. Bindings are very simple to use for predefine...
Olivier Beaudoux, Arnaud Blouin
JSS
2007
75views more  JSS 2007»
13 years 9 months ago
A rationale-based architecture model for design traceability and reasoning
Large systems often have a long life-span and comprise many intricately related elements. The verification and maintenance of these systems require a good understanding of their ...
Antony Tang, Yan Jin, Jun Han
NOCS
2008
IEEE
14 years 3 months ago
Network Simplicity for Latency Insensitive Cores
In this paper we examine a latency insensitive network composed of very fast and simple circuits that connects SoC cores that are also latency insensitive, de-synchronized, or asy...
Daniel Gebhardt, JunBok You, W. Scott Lee, Kenneth...