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DATE
2010
IEEE
174views Hardware» more  DATE 2010»
14 years 24 days ago
VAPRES: A Virtual Architecture for Partially Reconfigurable Embedded Systems
- Due to the runtime flexibility offered by field programmable gate arrays (FPGAs), FPGAs are popular devices for stream processing systems, since many stream processing applicatio...
Abelardo Jara-Berrocal, Ann Gordon-Ross
CGO
2003
IEEE
13 years 11 months ago
METRIC: Tracking Down Inefficiencies in the Memory Hierarchy via Binary Rewriting
In this paper, we present METRIC, an environment for determining memory inefficiencies by examining data traces. METRIC is designed to alter the performance behavior of applicatio...
Jaydeep Marathe, Frank Mueller, Tushar Mohan, Bron...
USENIX
1996
13 years 9 months ago
Transparent Fault Tolerance for Parallel Applications on Networks of Workstations
This paper describes a new method for providingtransparent fault tolerance for parallel applications on a network of workstations. We have designed our method in the context of sh...
Daniel J. Scales, Monica S. Lam
INFOCOM
1999
IEEE
13 years 12 months ago
Design and Performance of a Web Server Accelerator
We describe the design, implementation and performance of a Web server accelerator which runs on an embedded operating system and improves Web server performance by caching data. ...
Eric Levy-Abegnoli, Arun Iyengar, Junehwa Song, Da...
GLVLSI
2008
IEEE
140views VLSI» more  GLVLSI 2008»
14 years 2 months ago
A table-based method for single-pass cache optimization
Due to the large contribution of the memory subsystem to total system power, the memory subsystem is highly amenable to customization for reduced power/energy and/or improved perf...
Pablo Viana, Ann Gordon-Ross, Edna Barros, Frank V...