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TACO
2008
130views more  TACO 2008»
13 years 8 months ago
Efficient hardware code generation for FPGAs
r acceptance of FPGAs as a computing device requires a higher level of programming abstraction. ROCCC is an optimizing C to HDL compiler. We describe the code generation approach i...
Zhi Guo, Walid A. Najjar, Betul Buyukkurt
RSP
2005
IEEE
164views Control Systems» more  RSP 2005»
14 years 2 months ago
High Level Synthesis for Data-Driven Applications
Abstract— John von Neumann proposed his famous architecture in a context where hardware was very expensive and bulky. His goal was to maximize functionality with minimal hardware...
Etienne Bergeron, Xavier Saint-Mleux, Marc Feeley,...
LCPC
2007
Springer
14 years 2 months ago
Multidimensional Blocking in UPC
Abstract. Partitioned Global Address Space (PGAS) languages offer an attractive, high-productivity programming model for programming large-scale parallel machines. PGAS languages, ...
Christopher Barton, Calin Cascaval, George Alm&aac...
IWMM
2009
Springer
152views Hardware» more  IWMM 2009»
14 years 3 months ago
A new approach to parallelising tracing algorithms
Tracing algorithms visit reachable nodes in a graph and are central to activities such as garbage collection, marshalling etc. Traditional sequential algorithms use a worklist, re...
Cosmin E. Oancea, Alan Mycroft, Stephen M. Watt
IPPS
2003
IEEE
14 years 1 months ago
Extending OpenMP to Support Slipstream Execution Mode
OpenMP has emerged as a widely accepted standard for writing shared memory programs. Hardware-specific extensions such as data placement are usually needed to improve the scalabi...
Khaled Z. Ibrahim, Gregory T. Byrd