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» Data Memory Subsystem Resilient to Process Variations
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ICCD
2006
IEEE
124views Hardware» more  ICCD 2006»
14 years 4 months ago
Customizable Fault Tolerant Caches for Embedded Processors
Abstract— The continuing divergence of processor and memory speeds has led to the increasing reliance on larger caches which have become major consumers of area and power in embe...
Subramanian Ramaswamy, Sudhakar Yalamanchili
SIGCOMM
2010
ACM
13 years 7 months ago
R3: resilient routing reconfiguration
Network resiliency is crucial to IP network operations. Existing techniques to recover from one or a series of failures do not offer performance predictability and may cause serio...
Ye Wang, Hao Wang, Ajay Mahimkar, Richard Alimi, Y...
DSN
2007
IEEE
14 years 1 months ago
Utilizing Dynamically Coupled Cores to Form a Resilient Chip Multiprocessor
Aggressive CMOS scaling will make future chip multiprocessors (CMPs) increasingly susceptible to transient faults, hard errors, manufacturing defects, and process variations. Exis...
Christopher LaFrieda, Engin Ipek, José F. M...
DATE
2007
IEEE
100views Hardware» more  DATE 2007»
14 years 1 months ago
Working with process variation aware caches
Deep-submicron designs have to take care of process variation effects as variations in critical process parameters result in large variations in access latencies of hardware compo...
Madhu Mutyam, Narayanan Vijaykrishnan
SIGMOD
2012
ACM
345views Database» more  SIGMOD 2012»
11 years 10 months ago
Shark: fast data analysis using coarse-grained distributed memory
Shark is a research data analysis system built on a novel rained distributed shared-memory abstraction. Shark marries query processing with deep data analysis, providing a unifie...
Cliff Engle, Antonio Lupher, Reynold Xin, Matei Za...