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CODES
2007
IEEE
14 years 1 months ago
Compile-time decided instruction cache locking using worst-case execution paths
Caches are notorious for their unpredictability. It is difficult or even impossible to predict if a memory access results in a definite cache hit or miss. This unpredictability i...
Heiko Falk, Sascha Plazar, Henrik Theiling
EMSOFT
2007
Springer
14 years 1 months ago
Optimal task placement to improve cache performance
Most recent embedded systems use caches to improve their average performance. Current timing analyses are able to compute safe timing guarantees for these systems, if tasks are ru...
Gernot Gebhard, Sebastian Altmeyer
LCTRTS
2007
Springer
14 years 1 months ago
Generalizing parametric timing analysis
In the design of real-time and embedded systems, it is important to establish a bound on the worst-case execution time (WCET) of programs to assure via schedulability analysis tha...
Joel Coffman, Christopher A. Healy, Frank Mueller,...
LCTRTS
2007
Springer
14 years 1 months ago
Addressing instruction fetch bottlenecks by using an instruction register file
The Instruction Register File (IRF) is an architectural extension for providing improved access to frequently occurring instructions. An optimizing compiler can exploit an IRF by ...
Stephen Roderick Hines, Gary S. Tyson, David B. Wh...
GLOBECOM
2006
IEEE
14 years 1 months ago
Linear Coherent Decentralized Estimation
Abstract—We consider the distributed estimation of an unknown vector signal in a resource constrained sensor network with a fusion center. Due to power and bandwidth limitations,...
Jinjun Xiao, Shuguang Cui, Zhi-Quan Luo, Andrea J....