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» Data partitioning on chip multiprocessors
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ICCD
2004
IEEE
107views Hardware» more  ICCD 2004»
14 years 6 months ago
Analyzing Power Consumption of Message Passing Primitives in a Single-Chip Multiprocessor
In this work we propose a methodology for the accurate analysis of the power consumption of interprocessor communication in a MPSoC, and the construction of high-level power macro...
Mirko Loghi, Luca Benini, Massimo Poncino
FPL
2007
Springer
146views Hardware» more  FPL 2007»
14 years 4 months ago
Efficient External Memory Interface for Multi-processor Platforms Realized on FPGA Chips
The complexity of today’s embedded applications requires modern high-performance embedded System-on-Chip (SoC) platforms to be multiprocessor architectures. Advances in FPGA tec...
Hristo Nikolov, Todor Stefanov, Ed F. Deprettere
SIGARCH
2008
94views more  SIGARCH 2008»
13 years 9 months ago
Parallelization, performance analysis, and algorithm consideration of Hough transform on chip multiprocessors
This paper presents a parallelization framework for emerging applications on the future chip multiprocessors (CMPs). With the continuing prevalence of CMP and the number of on-die...
Wenlong Li, Yen-Kuang Chen
IEEEPACT
2008
IEEE
14 years 4 months ago
Improving support for locality and fine-grain sharing in chip multiprocessors
Both commercial and scientific workloads benefit from concurrency and exhibit data sharing across threads/processes. The resulting sharing patterns are often fine-grain, with t...
Hemayet Hossain, Sandhya Dwarkadas, Michael C. Hua...
ISCA
2007
IEEE
161views Hardware» more  ISCA 2007»
14 years 4 months ago
Physical simulation for animation and visual effects: parallelization and characterization for chip multiprocessors
We explore the emerging application area of physics-based simulation for computer animation and visual special effects. In particular, we examine its parallelization potential and...
Christopher J. Hughes, Radek Grzeszczuk, Eftychios...