Efficient External Memory Interface for Multi-processor Platforms Realized on FPGA Chips

The complexity of today’s embedded applications requires modern high-performance embedded System-on-Chip (SoC) platforms to be multiprocessor architectures. Advances in FPGA technology make the implementation of such architectures in a single chip (MPSoC) feasible and very appealing. In recent years, the FPGA vendors integrated enormous amount of hardware resources in their FPGAs allowing larger and more complex MPSoCs to be built in their FPGA fabric. The main limitation on the size of an MPSoC that can be built in a single FPGA appears to be the amount of onchip memory. To relax this limitation, the usage of external (off-chip) memory has to be considered. The state-of-the-art development tools support off-chip memory for (multi-master) shared bus architectures with arbitration of the memory accesses. Such architectures might be efficient for single processor systems however for multiprocessor systems the shared bus concept significantly limits the systems performance even if a ...

• Type: Conference
• Year: 2007
• Where: FPL
• Authors: Hristo Nikolov, Todor Stefanov, Ed F. Deprettere
• Keywords: FPGA, FPL 2007, Hardware, Hierarchical Memory, Multiprocessor Architectures