244 search results - page 25 / 49 » Data partitioning on chip multiprocessors |
NOCS
2008
IEEE
14 years 1 months ago
2008
IEEE
We present a methodology to debug a SOC by concentrating on its communication. Our extended communication model includes a) multiple signal groups per interface protocol at each I...
EUROPAR
2010
Springer
13 years 7 months ago
2010
Springer
Abstract. Limited bandwidth to off-chip main memory is a performance bottleneck in chip multiprocessors for streaming computations, such as Cell/B.E., and this will become even mor...
PPL
2006
13 years 6 months ago
2006
This paper analyses the micro-threaded model of concurrency making comparisons with both data and instruction-level concurrency. The model is fine grain and provides synchronisati...
ICPP
1998
IEEE
13 years 11 months ago
1998
IEEE
Exploiting locality at run-time is a complementary approach to a compiler approach for those applications with dynamic memory access patterns. This paper proposes a memory-layout ...
ISCA
2010
IEEE
13 years 11 months ago
2010
IEEE
Chip Multiprocessors (CMPs) are now commodity hardware, but commoditization of parallel software remains elusive. In the near term, the current trend of increased coreper-socket c...