Sciweavers

244 search results - page 35 / 49
» Data partitioning on chip multiprocessors
Sort
View
PPOPP
1990
ACM
13 years 10 months ago
Employing Register Channels for the Exploitation of Instruction Level Parallelism
Abstract - A multiprocessor system capable of exploiting fine-grained parallelism must support efficient synchronization and data passing mechanisms. This paper demonstrates the us...
Rajiv Gupta
CODES
2008
IEEE
14 years 1 months ago
A security monitoring service for NoCs
As computing and communications increasingly pervade our lives, security and protection of sensitive data and systems are emerging as extremely important issues. Networks-onChip (...
Leandro Fiorin, Gianluca Palermo, Cristina Silvano
ISHPC
2003
Springer
13 years 12 months ago
Code and Data Transformations for Improving Shared Cache Performance on SMT Processors
Simultaneous multithreaded processors use shared on-chip caches, which yield better cost-performance ratios. Sharing a cache between simultaneously executing threads causes excessi...
Dimitrios S. Nikolopoulos
VTC
2010
IEEE
159views Communications» more  VTC 2010»
13 years 5 months ago
Architectural Analysis of a Smart DMA Controller for Protocol Stack Acceleration in LTE Terminals
—In this paper we present an architectural analysis of a smart DMA (sDMA) controller for protocol stack acceleration in mobile devices supporting 3GPP’s Long Term Evolution (LT...
Sebastian Hessel, David Szczesny, Felix Bruns, Att...
IEEEPACT
2008
IEEE
14 years 1 months ago
Distributed cooperative caching
This paper presents the Distributed Cooperative Caching, a scalable and energy-efficient scheme to manage chip multiprocessor (CMP) cache resources. The proposed configuration is...
Enric Herrero, José González, Ramon ...