244 search results - page 45 / 49 » Data partitioning on chip multiprocessors |
HPCA
2009
IEEE
14 years 7 months ago
2009
IEEE
Performance and power consumption of an on-chip interconnect that forms the backbone of Chip Multiprocessors (CMPs), are directly influenced by the underlying network topology. Bo...
INFOCOM
2007
IEEE
14 years 1 months ago
2007
IEEE
Abstract—Deep packet inspection (DPI) is often used in network intrusion detection and prevention systems (NIDPS), where incoming packet payloads are compared against known attac...
DAC
2006
ACM
14 years 7 months ago
2006
ACM
Networks-on-Chip (NoC) architectures provide a scalable solution to on-chip communication problem but the bandwidth offered by NoCs can be utilized efficiently only in presence of...
ISCA
2009
IEEE
14 years 1 months ago
2009
IEEE
As transistor density continues to grow at an exponential rate in accordance to Moore’s law, the goal for many Chip Multi-Processor (CMP) systems is to scale the number of on-ch...
IEEEPACT
2008
IEEE
14 years 1 months ago
2008
IEEE
Communication overheads are one of the fundamental challenges in a multiprocessor system. As the number of processors on a chip increases, communication overheads and the distribu...