4278 search results - page 803 / 856 » Data prefetch mechanisms |
135
Voted
IPCCC
2006
IEEE
15 years 9 months ago
2006
IEEE
Low power has been considered as an important issue in instruction cache (I-cache) designs. Several studies have shown that the I-cache can be tuned to reduce power. These techniq...
120
Voted
IPPS
2006
IEEE
15 years 9 months ago
2006
IEEE
By violating MAC-layer protocols, the jamming attack aims at blocking successful communication among wireless nodes. Wireless sensor networks (WSNs) are highly vulnerable to jammi...
112
Voted
MICRO
2006
IEEE
15 years 9 months ago
2006
IEEE
The large working sets of commercial and scientific workloads stress the L2 caches of Chip Multiprocessors (CMPs). Some CMPs use a shared L2 cache to maximize the on-chip cache c...
120
Voted
MICRO
2006
IEEE
15 years 9 months ago
2006
IEEE
To protect processor logic from soft errors, multicore redundant architectures execute two copies of a program on separate cores of a chip multiprocessor (CMP). Maintaining identi...
161
Voted
RTSS
2006
IEEE
15 years 9 months ago
2006
IEEE
Location services are essential to many applications running on a hybrid of wirelessly-networked mobile actors and static sensors, such as surveillance systems and the Pursuer and...