67 search results - page 5 / 14 » Data transformations enabling loop vectorization on multithr... |
MICRO
1998
IEEE
13 years 11 months ago
1998
IEEE
We present an architecture that features dynamic multithreading execution of a single program. Threads are created automatically by hardware at procedure and loop boundaries and e...
JUCS
2000
13 years 7 months ago
2000
: Since the era of vector and pipelined computing, the computational speed is limited by the memory access time. Faster caches and more cache levels are used to bridge the growing ...
CGO
2004
IEEE
13 years 11 months ago
2004
IEEE
In this paper, we describe a generalized approach to deriving a custom data layout in multiple memory banks for array-based computations, to facilitate high-bandwidth parallel mem...
FPL
2009
Springer
14 years 2 days ago
2009
Springer
Commercial soft processors are unable to effectively exploit the data parallelism present in many embedded systems workloads, requiring FPGA designers to exploit it (laboriously) ...
MICRO
2003
IEEE
14 years 22 days ago
2003
IEEE
Data-parallel programs are both growing in importance and increasing in diversity, resulting in specialized processors targeted at specific classes of these programs. This paper ...