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DASIP
2010
13 years 3 months ago
High level design space exploration of RVC codec specifications for multi-core heterogeneous platforms
Nowadays, the design flow of complex signal processing embedded systems starts with a specification of the application by means of a large and sequential program (usually in C/C++...
Christophe Lucarz, Ghislain Roquier, Marco Mattave...
DSD
2006
IEEE
109views Hardware» more  DSD 2006»
14 years 3 months ago
ATOMI II - Framework for Easy Building of Object-oriented Embedded Systems
Traditionally, an embedded system design process demands a considerable amount of expertise, time and money. This makes developing embedded systems difficult for many companies, a...
Tero Vallius, Juha Röning
MICRO
2005
IEEE
140views Hardware» more  MICRO 2005»
14 years 2 months ago
Dynamic Helper Threaded Prefetching on the Sun UltraSPARC CMP Processor
Data prefetching via helper threading has been extensively investigated on Simultaneous MultiThreading (SMT) or Virtual Multi-Threading (VMT) architectures. Although reportedly la...
Jiwei Lu, Abhinav Das, Wei-Chung Hsu, Khoa Nguyen,...
DATE
2003
IEEE
104views Hardware» more  DATE 2003»
14 years 2 months ago
Efficient Field Processing Cores in an Innovative Protocol Processor System-on-Chip
We present an innovative protocol processor component that combines wire-speed processing for low-level, and best effort processing for higher-level protocols. The component is a ...
George Lykakis, N. Mouratidis, Kyriakos Vlachos, N...
IJCNN
2000
IEEE
14 years 1 months ago
Simulation of a Digital Neuro-Chip for Spiking Neural Networks
: Conventional hardware platforms are far from reaching real-time simulation requirements of complex spiking neural networks (SNN). Therefore we designed an accelerator board with ...
Tim Schönauer, S. Atasoy, N. Mehrtash, Heinri...