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ASPDAC
2007
ACM
122views Hardware» more  ASPDAC 2007»
13 years 11 months ago
A Novel Reconfigurable Low Power Distributed Arithmetic Architecture for Multimedia Applications
- The use of reconfigurable cores in system on chip (SoC) designs is increasingly becoming a trend. Such cores are being used for their flexibility, powerful functionality and low ...
Zhenyu Liu, Tughrul Arslan, Ahmet T. Erdogan
MSV
2004
13 years 9 months ago
Towards Quality of Service Based Resource Management for Cluster-Based Image Database
The main research in the area of image databases addresses the improvement of retrieval quality and the speedup of the query processing. A number of image retrieval systems reache...
Andreas Brüning, Frank Drews, Martin Hoefer, ...
ISCAS
2008
IEEE
109views Hardware» more  ISCAS 2008»
14 years 2 months ago
A low-area interconnect architecture for chip multiprocessors
— A new inter-processor communication architecture for chip multiprocessors is proposed which has a low area cost and flexible routing capability. To achieve a low area cost, th...
Zhiyi Yu, Bevan M. Baas
SIPS
2007
IEEE
14 years 1 months ago
An Area-Efficient FPGA-Based Architecture for Fully-Parallel Stochastic LDPC Decoding
Stochastic decoding is a new alternative method for low complexity decoding of error-correcting codes. This paper presents the first hardware architecture for stochastic decoding...
Saeed Sharifi Tehrani, Shie Mannor, Warren J. Gros...
ICCD
2003
IEEE
113views Hardware» more  ICCD 2003»
14 years 29 days ago
Multiple Transition Model and Enhanced Boundary Scan Architecture to Test Interconnects for Signal Integrity
As the technology is shrinking toward 50 nm and the working frequency is going into multi gigahertz range, the effect of interconnects on functionality and performance of system-o...
Mohammad H. Tehranipour, Nisar Ahmed, Mehrdad Nour...