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DATE
2002
IEEE
118views Hardware» more  DATE 2002»
15 years 8 months ago
A Complete Data Scheduler for Multi-Context Reconfigurable Architectures
: A new technique is presented in this paper to improve the efficiency of data scheduling for multi-context reconfigurable architectures targeting multimedia and DSP applications. ...
Marcos Sanchez-Elez, Milagros Fernández, Ra...
ISSS
2002
IEEE
126views Hardware» more  ISSS 2002»
15 years 8 months ago
Unifying Memory and Processor Wrapper Architecture in Multiprocessor SoC Design
In this paper, we present a new methodology for application specific multiprocessor system-on-chip design. This approach facilitates the integration of existing components with th...
Ahmed Amine Jerraya, Damien Lyonnard, Samy Meftali...
MICRO
1994
IEEE
81views Hardware» more  MICRO 1994»
15 years 7 months ago
Register file port requirements of transport triggered architectures
Exploitation of large amounts of instruction level parallelism requires a large amount of connectivity between the shared register file and the function units; this connectivity i...
Jan Hoogerbrugge, Henk Corporaal
ICCAD
1995
IEEE
106views Hardware» more  ICCAD 1995»
15 years 7 months ago
Re-engineering of timing constrained placements for regular architectures
In a typical design ow, the design may be altered slightly several times after the initial design cycle according to minor changes in the design speci cation either as a result o...
Anmol Mathur, K. C. Chen, C. L. Liu
ECBS
2008
IEEE
126views Hardware» more  ECBS 2008»
15 years 5 months ago
ALI: An Extensible Architecture Description Language for Industrial Applications
While Architecture Description Languages (ADLs) have gained wide acceptance in the research community as a means of describing system designs, the uptake in industry has been slow...
Rabih Bashroush, Ivor T. A. Spence, Peter Kilpatri...