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128
Voted
DATE
2005
IEEE
15 years 9 months ago
2005
IEEE
— This paper suggests a methodology to decrease the power of a static CMOS standard cell design at layout level by focusing on switched capacitance. The term switched is the key:...
98
Voted
DATE
2003
IEEE
15 years 9 months ago
2003
IEEE
We present a framework that considers global routing, repeater insertion, and flip-flop relocation for early interconnect planning. We formulate the interconnect retiming and ...
70
Voted
DATE
2003
IEEE
15 years 9 months ago
2003
IEEE
To increase the bandwidth of high-performance intrasystem interconnections optical multimode waveguides can be used. Since the design procedure of optical interconnections has to ...
129
Voted
DATE
2003
IEEE
15 years 9 months ago
2003
IEEE
Programming network processors remains an art due to the variety of different network processor architectures and due to little support to reason and explore implementations on su...
141
Voted
DATE
2003
IEEE
15 years 9 months ago
2003
IEEE
More and more the system verification makes use of hardware emulation techniques that allow a speed up in simulation performance up to thousand times. Typically, a design is comp...