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DATE
2006
IEEE
127views Hardware» more  DATE 2006»
15 years 10 months ago
ASIP architecture for multi-standard wireless terminals
This paper presents the Block Processing Engine (BPE), an Application Specific Instruction-Set Processor (ASIP) explicitly designed for the implementation of multistandard wireles...
Daniele Lo Iacono, J. Zory, Ettore Messina, N. Pia...
DATE
2006
IEEE
76views Hardware» more  DATE 2006»
15 years 10 months ago
Performance optimization for energy-aware adaptive checkpointing in embedded real-time systems
Using additional store-checkpoinsts (SCPs) and compare-checkpoints (CCPs), we present an adaptive checkpointing for double modular redundancy (DMR) in this paper. The proposed app...
Zhongwen Li, Hong Chen, Shui Yu
DATE
2006
IEEE
94views Hardware» more  DATE 2006»
15 years 10 months ago
Procrastinating voltage scheduling with discrete frequency sets
This paper presents an efficient method to find the optimal intra-task voltage/frequency scheduling for single tasks in practical real-time systems using statistical workload in...
Zhijian Lu, Yan Zhang, Mircea R. Stan, John Lach, ...
DATE
2006
IEEE
105views Hardware» more  DATE 2006»
15 years 10 months ago
Comfortable modeling of complex reactive systems
Modeling systems based on semi-formal graphical formalisms, such as Statecharts, has become standard practice in the design of reactive embedded devices. However, the modeling of ...
Steffen Prochnow, Reinhard von Hanxleden
DATE
2006
IEEE
159views Hardware» more  DATE 2006»
15 years 10 months ago
Distributed loop controller architecture for multi-threading in uni-threaded VLIW processors
Reduced energy consumption is one of the most important design goals for embedded application domains like wireless, multimedia and biomedical. Instruction memory hierarchy has be...
Praveen Raghavan, Andy Lambrechts, Murali Jayapala...