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DATE
2005
IEEE
101views Hardware» more  DATE 2005»
15 years 9 months ago
TSUNAMI: An Integrated Timing-Driven Place And Route Research Platform
In this paper, we present an experimental integrated platform for the research, development and evaluation of new VLSI back-end algorithms and design flows. Interconnect scaling ...
Christophe Alexandre, Hugo Clément, Jean-Pa...
DATE
2005
IEEE
110views Hardware» more  DATE 2005»
15 years 9 months ago
Test Time Reduction Reusing Multiple Processors in a Network-on-Chip Based Architecture
The increasing complexity and the short life cycles of embedded systems are pushing the current system-onchip designs towards a rapid increasing on the number of programmable proc...
Alexandre M. Amory, Marcelo Lubaszewski, Fernando ...
DATE
2005
IEEE
168views Hardware» more  DATE 2005»
15 years 9 months ago
Hardware Acceleration of Hidden Markov Model Decoding for Person Detection
This paper explores methods for hardware acceleration of Hidden Markov Model (HMM) decoding for the detection of persons in still images. Our architecture exploits the inherent st...
Suhaib A. Fahmy, Peter Y. K. Cheung, Wayne Luk
DATE
2005
IEEE
100views Hardware» more  DATE 2005»
15 years 9 months ago
Modeling the Non-Linear Behavior of Library Cells for an Accurate Static Noise Analysis
In signal integrity analysis, the joint effect of propagated noise through library cells, and of the noise injected on a quiet net by neighboring switching nets through coupling c...
Cristiano Forzan, Davide Pandini
DATE
2005
IEEE
165views Hardware» more  DATE 2005»
15 years 9 months ago
Flexible Hardware/Software Support for Message Passing on a Distributed Shared Memory Architecture
With the advent of multi-processor systems on a chip, the interest for message passing libraries has revived. Message passing helps in mastering the design complexity of parallel ...
Francesco Poletti, Antonio Poggiali, Paul Marchal