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131
Voted
DATE
2003
IEEE
15 years 9 months ago
2003
IEEE
In this paper we propose a design technique to pipeline cache memories for high bandwidth applications. With the scaling of technology cache access latencies are multiple clock cy...
138
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DATE
2003
IEEE
15 years 9 months ago
2003
IEEE
In this paper, a simulation-based synthesis tool, AMIGO, for analog cell sizing is presented. AMIGO is based upon genetic optimization techniques adapted to circuit sizing. A fram...
117
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DATE
2003
IEEE
15 years 9 months ago
2003
IEEE
In today’s deep-submicron designs, the interconnect delays contribute an increasing part to the overall performance of an implementation. Particularly when targeting field prog...
142
Voted
DATE
2003
IEEE
15 years 9 months ago
2003
IEEE
The design of clock distribution networks in synchronous digital systems presents enormous challenges. Controlling the clock signal delay in the presence of various noise sources,...
111
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DATE
2010
IEEE
15 years 9 months ago
2010
IEEE
— A new sub-space max-monomial modeling scheme for CMOS transistors in sub-micron technologies is proposed to improve the modeling accuracy. Major electrical parameters of CMOS...