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DATE
2002
IEEE
95views Hardware» more  DATE 2002»
15 years 10 months ago
Optimal Transistor Tapering for High-Speed CMOS Circuits
Transistor tapering is a widely used technique applied to optimize the geometries of CMOS transistors in highperformance circuit design with a view to minimizing the delay of a FE...
Li Ding 0002, Pinaki Mazumder
DATE
2002
IEEE
166views Hardware» more  DATE 2002»
15 years 10 months ago
Event Model Interfaces for Heterogeneous System Analysis
Complex embedded systems consist of hardware and software components from different domains, such as control and signal processing, many of them supplied by different IP vendors. ...
Kai Richter, Rolf Ernst
DATE
2000
IEEE
110views Hardware» more  DATE 2000»
15 years 10 months ago
Stochastic Modeling and Performance Evaluation for Digital Clock and Data Recovery Circuits
Clock and data recovery circuits are essential components in communication systems. They directly influence the bit-error-rate performance of communication links. It is desirable...
Alper Demir, Peter Feldmann
DATE
2000
IEEE
136views Hardware» more  DATE 2000»
15 years 10 months ago
On Applying Incremental Satisfiability to Delay Fault Testing
The Boolean satisfiability problem (SAT) has various applications in electronic design automation (EDA) fields such as testing, timing analysis and logic verification. SAT has bee...
Joonyoung Kim, Jesse Whittemore, Karem A. Sakallah...
DATE
2000
IEEE
140views Hardware» more  DATE 2000»
15 years 10 months ago
Parallel and Distributed VHDL Simulation
This paper presents a methodology for parallel and distributed simulation of VHDL using the PDES (parallel discrete-event simulation) paradigm. To achieve better features and perf...
Dragos Lungeanu, C.-J. Richard Shi