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DATE
2010
IEEE
154views Hardware» more  DATE 2010»
14 years 3 months ago
ERSA: Error Resilient System Architecture for probabilistic applications
There is a growing concern about the increasing vulnerability of future computing systems to errors in the underlying hardware. Traditional redundancy techniques are expensive for...
Larkhoon Leem, Hyungmin Cho, Jason Bau, Quinn A. J...
DATE
2010
IEEE
149views Hardware» more  DATE 2010»
14 years 3 months ago
Integrated end-to-end timing analysis of networked AUTOSAR-compliant systems
—As Electronic Control Units (ECUs) and embedded software functions within an automobile keep increasing in number, the scale and complexity of automotive embedded systems is gro...
Karthik Lakshmanan, Gaurav Bhatia, Ragunathan Rajk...
DATE
2010
IEEE
193views Hardware» more  DATE 2010»
14 years 3 months ago
Coordinated resource optimization in behavioral synthesis
Abstract—Reducing resource usage is one of the most important optimization objectives in behavioral synthesis due to its direct impact on power, performance and cost. The datapat...
Jason Cong, Bin Liu, Junjuan Xu
DATE
2002
IEEE
84views Hardware» more  DATE 2002»
14 years 2 months ago
Highly Scalable Dynamically Reconfigurable Systolic Ring-Architecture for DSP Applications
Microprocessors are today getting more and more inefficient for a growing range of applications. Its principles -The Von Neumann paradigm[3]- based on the sequential execution of ...
Gilles Sassatelli, Lionel Torres, Pascal Benoit, T...
DATE
2010
IEEE
175views Hardware» more  DATE 2010»
14 years 2 months ago
Approximate logic synthesis for error tolerant applications
─ Error tolerance formally captures the notion that – for a wide variety of applications including audio, video, graphics, and wireless communications – a defective chip that...
Doochul Shin, Sandeep K. Gupta