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DATE
2005
IEEE
97views Hardware» more  DATE 2005»
15 years 9 months ago
Synchronization Processor Synthesis for Latency Insensitive Systems
In this paper we present our contribution in terms of synchronization processor for a SoC design methodology based on the theory of the latency insensitive systems (LIS) of Carlon...
Pierre Bomel, Eric Martin, Emmanuel Boutillon
DATE
2005
IEEE
155views Hardware» more  DATE 2005»
15 years 9 months ago
RTK-Spec TRON: A Simulation Model of an ITRON Based RTOS Kernel in SystemC
This paper presents the methodology and the modeling constructs we have developed to capture the real time aspects of RTOS simulation models in a System Level Design Language (SLD...
M. Abdelsalam Hassan, Keishi Sakanushi, Yoshinori ...
DATE
2005
IEEE
122views Hardware» more  DATE 2005»
15 years 9 months ago
Systematic Transaction Level Modeling of Embedded Systems with SystemC
This paper gives an overview of a transaction level modeling (TLM) design flow for straightforward embedded system design with SystemC. The goal is to systematically develop both...
Wolfgang Klingauf
114
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DATE
2003
IEEE
96views Hardware» more  DATE 2003»
15 years 8 months ago
A System to Validate and Certify Soft and Hard IP
With the increasing use of Intellectual Property (IP) in the semiconductor industry, the demand to verify IP for quality is high. This paper describes ipscreen, a software tool th...
Bernard Laurent, Thierry Karger
DATE
2003
IEEE
108views Hardware» more  DATE 2003»
15 years 8 months ago
EBIST: A Novel Test Generator with Built-In Fault Detection Capability
Abstract : A novel design methodology for test pattern generation in BIST is presented. Here faults and errors in the generator itself are detected. Two different design methodolog...
Dhiraj K. Pradhan, Chunsheng Liu, Krishnendu Chakr...