72 search results - page 8 / 15 » Debugging programs that use atomic blocks and transactional ... |
ISCA
2012
IEEE
11 years 9 months ago
2012
IEEE
Hybrid processors are HW/SW co-designed processors that leverage blocked-execution, the execution of regions of instructions as atomic blocks, to facilitate aggressive speculative...
SPAA
2010
ACM
14 years 5 days ago
2010
ACM
Transactional Memory (TM) is a promising technique that simplifies parallel programming for shared-memory applications. To date, most TM systems have been designed to efficientl...
POPL
2006
ACM
14 years 7 months ago
2006
ACM
The movement to multi-core processors increases the need for simpler, more robust parallel programming models. Atomic sections have been widely recognized for their ease of use. T...
ASPLOS
2004
ACM
14 years 24 days ago
2004
ACM
Transactional Coherence and Consistency (TCC) offers a way to simplify parallel programming by executing all code within transactions. In TCC systems, transactions serve as the fu...
ASPLOS
2006
ACM
14 years 1 months ago
2006
ACM
Nested transactional memory (TM) facilitates software composition by letting one module invoke another without either knowing whether the other uses transactions. Closed nested tr...