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» Decoupled Hardware Support for Distributed Shared Memory
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ICCAD
2007
IEEE
118views Hardware» more  ICCAD 2007»
14 years 5 months ago
Timing variation-aware high-level synthesis
—This work proposes a new yield computation technique dedicated to HLS, which is an essential component in timing variationaware HLS research field. The SSTAs used by the curren...
Jongyoon Jung, Taewhan Kim
IPPS
2010
IEEE
13 years 6 months ago
Scalable multi-pipeline architecture for high performance multi-pattern string matching
Multi-pattern string matching remains a major performance bottleneck in network intrusion detection and anti-virus systems for high-speed deep packet inspection (DPI). Although Aho...
Weirong Jiang, Yi-Hua Edward Yang, Viktor K. Prasa...
PLDI
2011
ACM
12 years 11 months ago
A case for an SC-preserving compiler
The most intuitive memory consistency model for shared-memory multi-threaded programming is sequential consistency (SC). However, current concurrent programming languages support ...
Daniel Marino, Abhayendra Singh, Todd D. Millstein...
WMPI
2004
ACM
14 years 2 months ago
The Opie compiler from row-major source to Morton-ordered matrices
The Opie Project aims to develop a compiler to transform C codes written for row-major matrix representation into equivalent codes for Morton-order matrix representation, and to a...
Steven T. Gabriel, David S. Wise
CODES
2005
IEEE
14 years 2 months ago
Spatial division multiplexing: a novel approach for guaranteed throughput on NoCs
To ensure low power consumption while maintaining flexibility and performance, future Systems-on-Chip (SoC) will combine several types of processor cores and data memory units of...
Anthony Leroy, Paul Marchal, Adelina Shickova, Fra...