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MICRO
2008
IEEE
137views Hardware» more  MICRO 2008»
13 years 7 months ago
Verification of chip multiprocessor memory systems using a relaxed scoreboard
Verification of chip multiprocessor memory systems remains challenging. While formal methods have been used to validate protocols, simulation is still the dominant method used to ...
Ofer Shacham, Megan Wachs, Alex Solomatnikov, Amin...
IWMM
2011
Springer
270views Hardware» more  IWMM 2011»
12 years 10 months ago
Memory management in NUMA multicore systems: trapped between cache contention and interconnect overhead
Multiprocessors based on processors with multiple cores usually include a non-uniform memory architecture (NUMA); even current 2-processor systems with 8 cores exhibit non-uniform...
Zoltan Majo, Thomas R. Gross
SI3D
2012
ACM
12 years 3 months ago
Surface based anti-aliasing
We present surface based anti-aliasing (SBAA), a new approach to real-time anti-aliasing for deferred renderers that improves the performance and lowers the memory requirements fo...
Marco Salvi, Kiril Vidimce
ISCA
2012
IEEE
279views Hardware» more  ISCA 2012»
11 years 10 months ago
Staged memory scheduling: Achieving high performance and scalability in heterogeneous systems
When multiple processor (CPU) cores and a GPU integrated together on the same chip share the off-chip main memory, requests from the GPU can heavily interfere with requests from t...
Rachata Ausavarungnirun, Kevin Kai-Wei Chang, Lava...
IPPS
2006
IEEE
14 years 1 months ago
An extensible global address space framework with decoupled task and data abstractions
ions Sriram Krishnamoorthy½ Umit Catalyurek¾ Jarek Nieplocha¿ Atanas Rountev½ P. Sadayappan½ ½ Dept. of Computer Science and Engineering, ¾ Dept. of Biomedical Informatics T...
Sriram Krishnamoorthy, Ümit V. Çataly&...